COMPUTER ARCHITECTURE AND ENGINEERING PPT,PDF
Lec No. | Lecture Topic Click on lecture for WEB cast | Notes | |||
1 | Introduction, 5 components of a computer | ||||
2 | Review of MIPS ISA, Performance | ||||
3 | Logic Design, Technology & Delay Modeling | ||||
First Sections | |||||
Prerequisite Quiz: In class | |||||
4 | Performance and the Design process | ||||
5 | High-Level design and FPGA | ||||
6 | Verilog (finished), Multiplication | ||||
7 | [Homework quiz #2 at beginning of lecture] Single-Cycle Processor | ||||
8 | Instruction Decode/Multicycle Processor | ||||
9 | Multiprogramming/Exceptions | ||||
10 | Exceptions (continued), Pipelining | ||||
11 | [Homework quiz #3 at beginning of lecture] Pipelining (Continued) | ||||
12 | Pipelining Control | ||||
13 | Static Scheduling and compiler optimizations | ||||
14 | Compiler Optimizations (continued), Dynamic Scheduling | ||||
15 | Tomasulo Scheduling | ||||
16 | [Homework quiz #4 at beginning of lecture] Dynamic Scheduling (Con't), Speculation | ||||
17 | Speculation (Con't) | ||||
18 | Speculation (Finished), Memory Technology | ||||
19 | Memory Technology | ||||
20 | Caches | ||||
21 | Virtual Memory | ||||
22 | Buses and I/O | ||||
23 | [Homework quiz #5 at beginning of lecture] I/O and Queueing theory | ||||
24 | Queueing Theory, I/O arrays | ||||
25 | Low Power Design, Intel Processors | ||||
26 | Quantum computing + Wrap-up Lecture: Look at all you have learned! | ||||
